000			01222nam a2200253 a 4500
003			AR-LpUFIB
005			20250311170541.0
008			230201s2019 xxua r 000 0 eng d
020			_a9780128119051
024	8		_aDIF-M1411 _b8304 _zDIF008436
040			_aAR-LpUFIB _bspa _cAR-LpUFIB
100	1		_aHennessy, John L.
245	1	0	_aComputer architecture : _ba quantitative approach
250			_a6th ed.
260			_aCambridge : _b Morgan Kaufmann, _cc2019
300			_axxix, 617, [284] p. : _bil.
500			_aIncluye índice y bibliografía.
505	0		_a 1. Fundamentals of Quantitative Design and Analysis -- 2. Memory Hierarchy Design -- 3. Instruction-Level Parallelism and Its Exploitation -- 4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures -- 5. Multiprocessors and Thread-Level Parallelism -- 6. The Warehouse-Scale Computer -- 7. Domain Specific Architectures -- Appendix A. Instruction Set Principles -- Appendix B. Review of Memory Hierarchy -- Appendix C. Pipelining: Basic and Intermediate Concepts -- References -- Index
650		4	_aARQUITECTURA DE COMPUTADORAS
700	1		_aGoldberg, David E.
700	1		_aPatterson, David A.
700	1		_aAsanovic, Krste
942			_cBK
999			_c58204 _d58204