Normal view MARC view ISBD view

Smith-Waterman protein search with OpenCL on an FPGA

By:

Rucci, Enzo

Contributor(s):

Material type: Article

ArticleDescription: 1 archivo (361,0 kB)Subject(s):

Online resources:

Click here to access online

Summary: The well-known Smith-Waterman (SW) algorithm is a high-sensitivity method for local alignments. Unfortunately, SW is expensive in terms of both execution time and memory usage, which makes it impractical in many scenarios. Previous research has shown that massively parallel architectures such as GPUs and FPGAs are able to mitigate the computational problems and achieve impressive speedups. In this paper we explore SW acceleration on an FPGA with OpenCL. We efficiently exploit data and thread-level parallelism on an Altera Stratix V FPGA, obtaining up to 39 GCUPS with less than 25 watt of power consumption.

Average rating: 0.0 (0 votes)

Holdings ( 1 )
Title notes ( 3 )

Holdings
Item type	Home library	Collection	Call number	URL	Status	Date due	Barcode
Capítulo de libro	Biblioteca de la Facultad de Informática	Biblioteca digital	A0831 (Browse shelf(Opens below))	Link to resource	Recurso en Línea

Browsing Biblioteca de la Facultad de Informática shelves, Collection: Biblioteca digital Close shelf browser (Hides shelf browser)

Previous								Next
Previous	A0828 Socializar el despliegue y seguimiento de procesos de negocios	A0829 Obtaining classification rules using lvqPSO	A0830 Self-monitoring of blood glucose : use, frequency drivers, and cost in Argentina	A0831 Smith-Waterman protein search with OpenCL on an FPGA	A0832 Sketching for designing enactive interactions	A0833 Sistemas ensambladores de objetos de aprendizaje : estado del arte	A0834 Sistemas de tiempo real distribuidos usando microcontroladores	Next

Formato de archivo PDF. -- Este documento es producción intelectual de la Facultad de Informática - UNLP (Colección BIPA/Biblioteca)

The well-known Smith-Waterman (SW) algorithm is a high-sensitivity method for local alignments. Unfortunately, SW is expensive in terms of both execution time and memory usage, which makes it impractical in many scenarios. Previous research has shown that massively parallel architectures such as GPUs and FPGAs are able to mitigate the computational problems and achieve impressive speedups. In this paper we explore SW acceleration on an FPGA with OpenCL. We efficiently exploit data and thread-level parallelism on an Altera Stratix V FPGA, obtaining up to 39 GCUPS with less than 25 watt of power consumption.

IEEE International Conference on Trust, Security and Privacy in Computing and Communications (14ta : 2015 : Helsinki, Finlandia)